1. Field of the Invention
Example embodiments of the present invention relate to a memory system, and more particularly, to a memory system including an on-die termination unit having an inductor.
2. Description of the Related Art
A line used to transmit a signal to and/or receive a signal from a memory system may be terminated using terminal resistance to suppress the reflection of a signal, caused at a receiving side and/or a transmitting side. Signal reflection may degrade signal integrity (SI) and may significantly degrade the performance of a memory system supporting high-speed data transmission.
In conventional memory systems, input/output (I/O) terminals of a memory controller and/or a DRAM may be embodied as on-die termination (ODT) units terminated by termination resistance. The termination resistance may be set to match the impedance in a transmission line.
A transmission line connected to a receiver of a receiving side may contain parasitic capacitance caused by input capacitance in the receiver and/or junction capacitance in a driver. The parasitic capacitance may cause the termination resistance to vary in response to a variation in an operating frequency of a memory system. Accordingly the termination resistance may not be substantially fixed if the termination resistance varies.
If a termination resistance in the I/O terminal is maintained at a constant value, a gain in the I/O terminal may be maintained at a constant value even if the operating frequency is changed from a low frequency to a high frequency. However, if a termination resistance in an I/O terminal varies with a parasitic capacitance, the gain in the I/O terminal may fluctuate.
To reduce and/or remove issues stemming from or relating to a parasitic capacitance and to realize broadband termination, ODT may require inductance. Signal integrity may be improved by adding an inductor into an ODT unit. However, because the size of an inductor is typically large, the addition of the inductor may significantly increase the chip size.